The technology press covers EUV lithography obsessively. Every new lens generation, every NA milestone, every wafer per hour improvement at ASML gets detailed coverage. That attention is deserved — lithography is genuinely the pacing constraint for transistor density scaling. But there's a second constraint, less visible and equally fundamental, that will determine whether sub-2nm logic devices actually deliver the performance improvements the roadmap promises. It's in the gate dielectric.
To understand why, you need to understand what the gate oxide does. In a MOSFET, the gate electrode controls the channel region via an electric field. The oxide between the gate and the channel is the medium through which that control operates. A thinner oxide means stronger gate control (higher capacitance), which allows the transistor to operate at lower voltages with faster switching. But a thinner oxide means more quantum mechanical tunneling of electrons through it — current that flows when the gate is supposed to be blocking. That's leakage, and leakage is power you can't recover.
The High-K Revolution and Its Limits
The semiconductor industry solved the SiO2 tunneling problem in 2007 when Intel introduced hafnium oxide (HfO2) as the gate dielectric — the "high-k metal gate" transition that Intel called a breakthrough comparable in significance to the introduction of the transistor itself. That characterization was accurate. By using a material with a higher dielectric constant (k) than SiO2, you can maintain the same gate capacitance with a physically thicker layer of oxide, reducing tunneling current by orders of magnitude.
HfO2 has a dielectric constant around 20-25, compared to SiO2's value of 3.9. That means a 2nm physical layer of HfO2 is electrostatically equivalent to a 0.4nm layer of SiO2 — described as an equivalent oxide thickness (EOT) of 0.4nm. You get strong gate control without the tunneling penalty of a 0.4nm physical SiO2 layer, which would be only 2-3 atomic layers thick and physically unstable.
Since 2007, the industry has continued scaling EOT down and improving HfO2 quality. We're currently at EOT values around 0.7-1.0nm in leading production processes. The target for sub-2nm gate-all-around devices is EOT below 0.5nm — possibly as low as 0.35nm for the most aggressive roadmap scenarios. And here's where the chemistry starts to fight back.
Why the Next 0.3nm Is Hard
HfO2 has a problem at very thin layers: it becomes polycrystalline. Below about 3nm physical thickness, hafnium oxide film deposited by atomic layer deposition (ALD) doesn't form a uniform amorphous structure — it crystallizes, with grain boundaries that become preferential paths for leakage current and diffusion of dopant atoms. The crystallization temperature is also uncomfortably close to standard thermal processing steps in the fab, meaning you can't always anneal away defects without inducing unwanted phase transitions.
The industry's response has been doping — adding small amounts of zirconium, aluminum, lanthanum, or other metals to HfO2 to stabilize the amorphous phase at thinner layers and tune the dielectric constant. This works, partially. Hafnium zirconium oxide (HZO) is now standard in production, and lanthanum-doped HfO2 has shown promising results for interface quality improvement. But you're adding process complexity, and the parameter space for multi-component oxide optimization is enormous.
The number of relevant process variables in ALD of doped hafnium oxides — precursor pulse sequences, temperatures, cycling ratios, surface passivation chemistry — exceeds what empirical process of elimination can efficiently optimize. This is a problem that benefits from computational materials science and machine learning over physical surfaces.
The second problem is the interface. Between the high-k dielectric and the silicon channel, there's an unavoidable interfacial layer — mostly SiO2 — that forms during deposition and annealing. This interfacial layer has a low dielectric constant, and its EOT contribution adds to the total. Controlling interfacial layer thickness and quality is currently one of the hardest process challenges at advanced nodes. OxideLayer, our Portland-based portfolio company, is specifically focused on ultra-thin gate oxide deposition for sub-2nm processes — building ALD process chemistry that minimizes interfacial layer growth while maintaining the bulk HfO2 film quality needed for low leakage.
The nanosheet Complication
Gate-all-around nanosheet transistors — the architecture that replaces FinFETs at 2nm and below — make the gate oxide problem harder in one specific way: you're depositing the oxide on all four sides of a suspended silicon nanosheet. The top, bottom, and side surfaces of the nanosheet have different surface chemistries, different defect densities, and respond differently to ALD precursors. Getting uniform EOT across all four surfaces is a conformality challenge that planar and FinFET geometries didn't present in the same way.
The nanosheet stack geometry also means you have very limited space between adjacent sheets in the vertical stack. Typical sheet-to-sheet spacing in production nanosheet devices is 8-12nm. After depositing the gate oxide and the gate metal, you need to fill the remaining space with the work-function metal that controls the threshold voltage. If the gate oxide is non-uniform or has thickness variations from the ALD process, the work-function metal fill has correspondingly less room to work with, and threshold voltage uniformity suffers — which means yield suffers.
Alternative Dielectrics and the 2028 Problem
The materials research community has been looking at alternatives to HfO2 for the next generation of devices. Candidates include high-k perovskite oxides (SrTiO3, BaTiO3, and related compounds) with dielectric constants above 100, which would allow dramatically thicker physical films at equivalent EOT. The challenge is that these materials are thermodynamically incompatible with silicon at standard processing temperatures — they react with silicon, they're hygroscopic, and their crystalline structures require substrates that don't match silicon's lattice constant.
Lanthanum aluminate (LaAlO3) has shown interesting results in academic work — high k, large bandgap, and better thermal stability than perovskites. Interface quality with silicon is still a challenge. Gadolinium oxide (Gd2O3) has been studied as an alternative with reasonable k and good interface properties. None of these are close to production at leading fabs.
The 2028 problem: that's roughly when sub-2nm production processes need to be in volume manufacturing to stay on the published roadmaps. The gate oxide chemistry has to be solved, qualified, and integrated into production processes in the next two to three years. Given fab qualification timelines, the solutions that will enter production by 2028 are largely being evaluated now. This is a very narrow window for materials innovation to intersect with fab adoption cycles.
We think that window creates a specific investment opportunity: companies with differentiated ALD chemistry or precursor synthesis capabilities for advanced dielectric films, who are already engaged with at least one major foundry in process qualification discussions. Those conversations take years to mature, which means the companies positioned to win are already in the room. Finding them before the qualification completes is the job.
Developing advanced gate dielectrics, ALD precursor chemistry, or thin-film characterization tools? Talk to Coexin.
