Next-gen RISC-V custom silicon for edge AI inference. ArborICS designs domain-specific processors that deliver datacenter inference performance in a 3W power envelope — a constraint no general-purpose chip has met. Headquartered in Austin, TX.
Error-corrected qubit arrays for financial modeling. QuantVault's surface-code architecture achieves logical error rates below 10-6, targeting Monte Carlo simulations that are intractable for classical hardware. Boston, MA.
Silicon photonics interconnects for AI data centers. Lumenwire replaces copper traces with on-chip photonic links, cutting cross-rack communication latency by 40% while reducing energy per bit to 0.5 pJ. San Jose, CA.
2D materials and heterostructures for next-gen transistors. Tesseract has demonstrated MoS2/hBN bilayers with channel mobility exceeding 400 cm²/Vs — a 3x improvement over strained silicon at equivalent node. Cambridge, MA.
Autonomous precision robots for semiconductor fabs. Seraph's six-axis wafer-handling robots operate in ISO Class 1 cleanrooms with positional repeatability under 2 microns — enabling touchless fab lines that reduce contamination-driven yield loss. Pittsburgh, PA.
Quantum key distribution for critical infrastructure. CrystalQNet's photon-pair source achieves entanglement fidelity above 99.1% over 120km dark fiber, making QKD practical for financial and government backbone networks. Berkeley, CA.
Ultra-thin gate oxide deposition for sub-2nm nodes. OxideLayer's ALD process deposits equivalent oxide thicknesses below 4 angstroms with interface trap densities that outperform current HfO2 baselines — unlocking the next node transition. Portland, OR.
Magnetic tunnel junction memory for neuromorphic chips. NovaSpin's STT-MRAM arrays switch in under 3 nanoseconds at write energies below 50 fJ per bit, giving neuromorphic processors the near-zero-latency memory they need to operate at synaptic speeds. Zurich / US entity.