Five years ago, the RISC-V argument was primarily theoretical. The ISA is open. Anyone can design a core. The licensable alternative from Arm costs money and comes with restrictions that matter for companies trying to build genuinely differentiated silicon. The counterargument was also reasonable: open doesn't mean ready. The IP ecosystem, EDA tool support, and software stack that Arm had built up over two decades would take years to replicate.
That gap has closed faster than most people expected. Not because the ISA is better in any fundamental sense — RISC-V and Arm are both clean, well-specified instruction set architectures — but because the economics of custom silicon have changed. Edge AI inference is a workload that rewards specialization in ways that general-purpose processors simply cannot match. When you're running a specific neural network topology on a specific piece of hardware at 5 watts, every unnecessary instruction, every unused pipeline stage, every byte of cache you don't need is dead silicon area and wasted power.
Why Domain-Specific Silicon Wins at the Edge
The cloud computing model taught everyone that compute is a commodity. That's true in the cloud. It's not true at the edge. A sensor node processing video for defect detection on a manufacturing line doesn't need to run arbitrary workloads. It needs to run one workload — or a small family of related workloads — with the lowest possible power envelope and the highest possible throughput on that specific task.
RISC-V's modularity is the key. The base integer ISA (RV32I or RV64I) is small and well-defined. Extensions are additive and optional. If you're building an inference accelerator, you add vector extensions for the SIMD operations that dominate neural network computation, you add custom instructions for the specific matrix dimensions your network uses, and you leave out everything else. The result is a core that's maybe 40% smaller than a general-purpose Arm Cortex-A series core running the same workload — and proportionally more power-efficient.
ArborICS, our Austin-based portfolio company, is building exactly this kind of specialized silicon. Their core is optimized for sub-8-bit quantized inference workloads, with custom datapath extensions for the specific tensor operations that matter in lightweight convolutional networks. The die area savings relative to a standard RISC-V implementation running the same network are significant — north of 30% in our technical diligence — and the performance-per-watt numbers are competitive with dedicated neural network accelerators that have been in development for years longer.
The EDA Gap Is Real but Closing
Here's where the criticism of RISC-V still has teeth: the EDA toolchain. Synopsys, Cadence, and Mentor have decades of characterized libraries, optimized synthesis flows, and process design kits (PDKs) for Arm cores. RISC-V cores generally use open-source or less-mature tools, and the gap in optimized standard cell libraries for specific process nodes (say, TSMC N5 or N4P) is real. Companies doing leading-edge RISC-V silicon often spend engineering resources on the EDA side that an Arm-based design would not require.
But this is shrinking. TSMC and Samsung both now have dedicated RISC-V support programs. Synopsys added RISC-V support to its DesignWare IP portfolio. More importantly, the open-source EDA movement — tools like OpenROAD, which targets automated physical design from RTL to GDSII — is maturing enough that smaller teams can get to tape-out without the full $50M EDA license overhead that high-volume chip design traditionally required.
The RISC-V toolchain story is no longer "will this work." It's "how much engineering time does this cost compared to Arm." That gap is measured in weeks, not years.
The Market Structure Question
The interesting strategic question for RISC-V is not whether it can produce good chips — it can. The question is what the market structure looks like in five years. Arm's business model is IP licensing at scale. RISC-V doesn't change that for commodity consumer devices where Arm's software ecosystem lock-in is strongest: phones, tablets, laptops. Android and iOS are Arm ecosystems. That's not going to flip.
The market that RISC-V genuinely disrupts is industrial, automotive, and IoT edge compute — applications where the software ecosystem is less critical than the hardware customization, where lifecycle requirements often exceed Arm's licensing terms, and where the total addressable market is fragmented into thousands of specific applications rather than a handful of dominant platform types.
That's a large market. Automotive semiconductor content per vehicle is growing at 12-15% annually. Industrial IoT connected devices number in the tens of billions. Defense and aerospace applications for specialized inference silicon are growing. None of these buyers want to pay an ISA licensing royalty forever on hardware that will sit in a piece of industrial equipment for 15 years.
Where We're Placing Bets
We're not interested in another RISC-V core IP vendor — the competition there is already intense and the margins on ISA licensing alone are thin. The interesting positions are at the system level: companies that bundle a RISC-V core with domain-specific peripherals and accelerators into a complete chiplet that solves a specific vertical's problem. Think sensor fusion for autonomous vehicles, real-time control for robotic joints, or sub-milliwatt inference for continuous health monitoring sensors.
The second interesting position is in the software and toolchain layer. Custom silicon only works if the firmware and inference runtime are optimized for the specific core configuration. Companies that deliver silicon plus optimized software stack for a target application are building a much stickier product than bare die. Once a customer's application is compiled and tuned for your ISA extensions, switching costs are high. That's a durable moat that pure hardware vendors rarely have.
The third — and most contrarian — bet is in verification and testing infrastructure. Custom silicon has custom bugs. The verification effort for a RISC-V design with proprietary extensions is larger and less automated than for a standard Arm core where decades of regression suites exist. Companies building efficient RISC-V verification flows, formal verification tools for custom extensions, and post-silicon debug environments are solving a real engineering bottleneck that every custom silicon team faces.
If you're designing custom silicon for edge inference or building RISC-V tooling, we want to talk. Reach the Coexin team.
