Early-stage semiconductor founders are, as a class, extraordinary engineers. They understand their device physics in depth — the band structure choices that motivate their materials selection, the gate dielectric tradeoffs that enable their operating voltage targets, the interconnect topology that achieves their bandwidth numbers. What they often understand less well is the industrial process that will translate their device design into working silicon at the price point their business model requires.
This asymmetry is not surprising. Deep device expertise is what gets a startup funded at the seed stage. Yield models are the province of process integration engineers at mature fabs — skills that are hard to hire outside of the companies that monopolize advanced process nodes. But by the time a semiconductor startup reaches Series A, the foundry question has become the question. How Coexin evaluates process risk in early-stage diligence is the subject of this memo.
Yield Is a Cost Model, Not a Technical Achievement
The standard way yield gets discussed in pitch decks is as a performance threshold: "our process achieves X% yield on characterization structures." This framing conflates two distinct questions. The first is whether the device works — whether the process produces functional transistors, waveguides, or qubits meeting specification. The second is whether the economics work — whether the cost per working unit at the required volume fits the product's margin structure.
These questions diverge dramatically as die size increases. Yield follows a Poisson-statistics-based model: for a die of area A manufactured at a process node with a defect density D defects per cm², the expected yield is approximately exp(−A × D). For small dies — say, 5 mm² on a mature process node — even a defect density of 0.1 per cm² gives yields above 95%. For a large AI accelerator at 800 mm² on a leading-edge node with a defect density of 0.05 per cm², the same formula gives a yield of approximately 2%. The economics of selling a chip at that yield are completely different from anything the founders' prior experience at system-level companies would suggest.
Large-die chips are not just harder to make — they have a fundamentally different cost structure. Every foundry run that improves yield by 10 percentage points at the 2% baseline has the same dollar impact as a 500% improvement at the 95% baseline. The sensitivity of unit economics to yield is non-linear in a way that catches founders off guard.
The Three Fab Strategy Archetypes
Semiconductor startups broadly choose between three foundry strategies, each with a distinct risk profile. The first is commodity CMOS fabrication at a mature node: processes in the 28nm to 180nm range, available from multiple foundries, well-characterized defect densities, and predictable pricing. This is the right choice for microcontrollers, analog mixed-signal chips, and power management silicon where the device does not require the most advanced lithography. The engineering risk is low; the competitive risk is that the process is available to any competitor.
The second archetype is advanced CMOS on a leading-edge node: 3nm to 7nm processes available from a small number of foundries, each with proprietary process design kits (PDKs). The advantage is density — more transistors per mm², enabling lower power for a given compute throughput, or more compute for a given die area. The risk is the combination of high mask-set costs (typically $5M to $15M for a complete mask set at 5nm), long turnaround times (4 to 8 months per tapeout), limited foundry slots, and the process expertise that exists only inside the foundry itself. Debugging yield issues at advanced nodes requires access to characterization data that foundries share selectively, and the startup founder is negotiating for that access from a weak position.
The third archetype is a specialized or novel process: silicon photonics, GaN power electronics, superconducting Josephson junction circuits, or quantum dot arrays. These processes are not available from the major commodity foundries. They require either a relationship with a specialty foundry (of which there are a small number globally) or internal fab capability. The risk profile here is extreme: the startup is simultaneously developing a novel device technology and learning a manufacturing process that has no established high-volume baseline. Defect densities are not well-characterized because the process has not been run at high volume. Yield models are educated guesses.
How Coexin Evaluates Foundry Risk
In our diligence on semiconductor startups, the foundry risk evaluation runs along four axes. The first is tapeout history: has the team successfully taped out at the target foundry on a comparable process, and what was the yield of that run? One successful tapeout does not guarantee the next will work — process drift, mask quality variation, and lot-to-lot recipe inconsistencies are real — but teams with multiple successful tapeouts at a foundry have demonstrated they can navigate the process design kit and debug yield issues collaboratively with the foundry process integration team.
The second axis is foundry relationship depth. A startup with a direct relationship to a process integration engineer at the foundry — not just a sales account manager — has meaningfully better access to the characterization data and engineering support needed to improve yield. This is partly a function of reputation (foundries prioritize engineering support for customers they expect to be long-term revenue), partly geography, and partly the backgrounds of the founding team. Teams that have spun out of foundry ecosystem companies tend to have these relationships; teams composed entirely of system-level engineers often do not.
The third axis is die size and process node sensitivity. We build a simple yield sensitivity model for every semiconductor investment: what does the unit economics look like at current yield, and what does the cost per die look like if yield improves by a factor of two, five, or ten? For companies where the business case is contingent on reaching yields that require multiple process optimization cycles — which typically means years and tens of millions of dollars of foundry engineering effort — the investment horizon and capital requirements are fundamentally different from a company whose business case works at current yield levels.
The fourth axis is optionality: can the company function at lower volume while yield ramps, or does the business model require high-volume production economics from day one? Cerebras Systems, a Coexin Fund I portfolio company, solved this problem in part by designing the Wafer-Scale Engine to be economically viable at extremely low unit volume — the chip occupies an entire 300mm wafer, so the per-wafer cost is not the constraint; the per-unit compute delivered per dollar is. This is an unusual case, but it illustrates how die size, yield, and business model can be designed to be coherent rather than in tension.
What Founders Should Do Before Series A
The practical advice for founders preparing for a Series A from a deep-tech semiconductor fund is specific. First: run a tapeout before the raise if at all possible. Working silicon, even at low yield and small die size, demonstrates that the team can navigate the process and provides real data on defect density. Simulated or modeled yield numbers are not useful for investor diligence; they tell us what the physics expects, not what the process delivers.
Second: build a yield model, not just a device model. What is your die area? What is the expected defect density on your target process? What is the resulting first-pass yield? What yield improvement do you need to achieve your target cost of goods sold, and what is your theory for how to achieve it — through design for manufacturability (DFM) optimization, process flow changes, or moving to a different node? Having thought carefully through these questions does not guarantee good outcomes, but it demonstrates the kind of manufacturing realism that distinguishes teams who have built products from teams who have built devices.
Third: understand what your foundry relationship actually is. Sales account managers and process integration engineers are different people with different information and different incentives. If you cannot name the process integration engineers at your foundry who will be responsible for your lot, you do not yet have the relationship that enables fast yield improvement. Building that relationship before you need it — during characterization runs, during pilot production — is significantly less expensive than trying to build it during a yield crisis.
This memo represents the views of the author. It does not constitute investment advice or a recommendation to buy or sell any security. References to portfolio companies are for illustrative purposes only.