Occasional long-form writing on semiconductor architecture, quantum hardware, and photonic compute — authored by Coexin partners. Not investment advice. Not market commentary. Technical analysis for founders and researchers building at the physical layer.
As neutral-atom platforms move from 256-qubit to 10,000-qubit arrays, the fidelity conversation changes. This memo unpacks what two-qubit gate fidelity of 99.5% means in practice for fault-tolerant computation — and why the threshold theorem is not a threshold you cross once.
Every new chip architecture gets benchmarked against NVIDIA's latest GPU and found wanting. That's the wrong frame. Reconfigurable dataflow architectures are solving a different problem — one that becomes more pronounced as model sizes scale past 1 trillion parameters.
Every semiconductor startup has a fab strategy. Most founders understand their device architecture better than their yield model. This memo explains why that asymmetry matters to investors — and how Coexin evaluates process risk in early-stage diligence.
Photonic interconnects have been 'five years away from commercial scale' for a decade. Several companies in the Coexin portfolio are proving that framing wrong. What changed — and what the remaining engineering challenges actually are.
The memory wall is not a software problem. This memo revisits why wafer-scale integration addresses a fundamental physical constraint that chiplet-based designs cannot fully solve — and what it costs to do so.
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